In an integrated circuit, a clock tree is generally used for distributing a common clock signal to various components in order to synchronize the operation thereof. Differences in the arrival time of the clock signals at two or more clocked components of the integrated circuit can result in errors in the operation of the integrated circuit. In some applications, the clock tree for the distribution of the common clock signal includes structures such as H-tree meshes or balanced buffer trees. In many cases, mismatch of the arrival of the distributed clock signals is minimized at the cost of sufficient driving current for distributing the common clock signal along the clock tree. With the increase of the frequency of the clock signal, power consumption for driving the clock tree increases. Also, clock buffers at various stages of the clock trees usually draw huge currents from a power supply grid, and thus affect the performance of nearby components by causing voltage drops of the supply voltage. In some applications, clock trees use 20% to 40% of total power consumption of the integrated circuits.